EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...
EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Design-Reuse

Adaptive Silicon and Atrenta Partner to Provide RTL Coding Rules for Programmable Logic Cores

LOS GATOS, Calif./SAN JOSE, Calif. - October 8, 2001 - Adaptive Silicon, Inc. (ASi) of Los Gatos, Calif., and Atrenta Inc. of San Jose, Calif., today announced that ASi is developing an Adaptive ...
Semiconductor Engineering

Multi-Modal AI In EDA Development Flows

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...