EDN

IEEE 1666 (SystemC) now includes TLM 2.0

When OSCI was formed and the SystemC language given to the industry, it created more controversy that anything else. Over time that subsided and people looked at SystemC as a potential new language to ...
Design-Reuse

OVP Simulator Smashes SystemC TLM-2.0 Performance Barrier

Thame, U.K. -- February 13, 2009-- Open Virtual Platforms (OVP) today released new native SystemC transaction level modeling (TLM)-2.0 technology to use with OVP CPU models that run to the speed of ...
Design-Reuse

The Open SystemC Initiative Announces Availability of the SystemC Transaction-level Modeling Standard with Broad Industry Support

SAN JOSE, Calif.--(BUSINESS WIRE)--June 6, 2005--The Open SystemC Initiative (OSCI) today announced the delivery of the SystemC(TM) Transaction-level Modeling (TLM) Standard 1.0. The availability of a ...
Business Wire

Reference Virtual Platform of ARM Model Running Linux Under SystemC/TLM-2.0 Released by Open Virtual Platforms (OVP)

THAME, England--(BUSINESS WIRE)--The Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has announced the release of a reference virtual platform of the ARM Integrator development board using ...
EDN

DESIGN FLOWS: Engineers write up SystemC TLM concepts

Santa Cruz, Calif. – Claiming to document a major step forward in system-on-chip design, STMicroelectronics engineers are writing a book about the SystemC transaction-level modeling the European ...
Semiconductor Engineering

Using SystemC TLM Modeling To Solve AI Data Movement Challenges

In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, ...
Semiconductor Engineering

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, ...
Business Wire

IEEE Approves Revised IEEE 1666™ “SystemC Language” Standard for Electronic System-Level Design, Adding Support for Transaction-level Modeling

PISCATAWAY, N.J.--(BUSINESS WIRE)--IEEE, the world's largest professional association advancing technology for humanity, today announced that the IEEE Standards Association (IEEE-SA) Standards Board ...
Electronic Design

SystemC Model Library Makes TLM Reuse Easier

Would-be users of transaction-level models (TLMs) and electronic system-level (ESL) design approaches in general face a major hurdle. Traditionally, it has been difficult to construct TLMs that serve ...
Electronic Design

IDE Lays SystemC Designs Bare For Easier Debugging

Sometimes design abstraction is a help, and sometimes it's a hindrance. Verification of system-on-a-chip designs with SystemC has a demonstrated ability to significantly speed up simulation runs.
uni

SystemC to Timed Automata Transformation Engine (STATE)

STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...