EDN

Testing and Debugging DSP Systems, Part 3

Part two explains the workings of the JTAG boundary-scan technology. Part four explains how to use breakpoints, event triggers, and program traces to debug code. Emulation is a technology used in the ...
Electronic Design

ARM On-Chip Debug Hardware

ARM, one of the twenty-first century microprocessor standards, has a major presence in SoCs. A 32-bit RISC, it was designed for mid- to low-level applications. It was also designed for low-power ...
EDN

JTAG 101 – Part 1: Overview and On-Chip Debug Methods

JTAG (jay-tag) is one of the engineering acronyms that has been transformed into a noun, although arguably it is not so popular as RAM, or CPU. IEEE Std 1149.1-1990 IEEE Standard Test Access Port and ...
Electronic Design

Build A Debug And Trace Systems For Multicore SoCs

Embedded designers put microprocessors in everyday products like cars, phones, cameras, TVs, music players, and printers, as well as the communications infrastructure, which the general public doesn’t ...
Business Wire

NI LabVIEW Toolkit Simplifies Design Validation and Debugging of TI DSPs - Engineers Control RTDX Communication in Seconds Using National Instruments LabVIEW

AUSTIN, Texas--(BUSINESS WIRE)--Sept. 16, 2003--National Instruments (Nasdaq:NATI) today announced the LabVIEW DSP Test Integration Toolkit 2.0, a LabVIEW add-on that integrates with Texas Instruments ...